BUGS:
    ✔ Branch instructions seem to jump to the wrong place @done(24-01-22 19:08)
        - looks like the offset should be able to be a negative value but it's not


General:
    ✔ Add unit tests for each instruction and address mode @done(23-11-07 19:57)
    ☐ Fully implement clock cycle tracking
    ☐ Add a disassembler for debugging
        ☐ Debug data lookup for instructions

Test Machine:
    ☐ Implement basic input
    ✔ Hello world program @done(24-01-19 17:09)
    ✔ Load and run a given program binary @done(24-01-22 17:08)

CPU:
    Signals:
        ✔ Clock @done(23-11-07 20:45)
        ✔ Reset @done(23-11-07 20:46)
        ✔ irq function @done(24-01-19 13:17)
        ✔ nmi function @done(24-01-19 13:17)

Addressing modes:
    ✔ IMP - Implied @done(23-11-07 14:01)
    ✔ IMM - Immediate @done(23-11-06 19:01)
    ✔ ZP0 - Zero Page @done(23-11-07 14:40)
    ✔ ZPX - Zero Page, X @done(23-11-07 14:40)
    ✔ ZPY - Zero Page, Y @done(23-11-07 14:40)
    ✔ REL - Relative @done(24-01-19 13:17)
        ✔ Code @done(23-11-07 20:44)
        ✔ Test @done(24-01-19 13:17)
    ✔ ABS - Absolute @done(23-11-07 20:25)
    ✔ ABX - Absolute, X @done(23-11-07 20:25)
    ✔ ABY - Absolute, Y @done(23-11-07 20:25)
    ✔ IND - Indirect @done(24-01-10 15:26)
    ✔ IZX - Indirect, X @done(24-01-10 15:26)
    ✔ IZY - Indirect, Y @done(24-01-10 15:26)

Instructions:
    GROUP ONE:
        ✔ 000	ORA @done(23-11-06 18:55)
        ✔ 001	AND @done(23-11-07 13:43)
        ✔ 010	EOR @done(23-11-07 13:43)
        ✔ 011	ADC @done(23-11-06 19:59)
        ✔ 100	STA @done(23-11-07 15:04)
        ✔ 101	LDA @done(23-11-06 18:55)
        ✔ 110	CMP @done(23-11-09 13:24)
        ✔ 111	SBC @done(23-11-09 13:24)

    GROUP TWO:
        ✔ 000	ASL @done(23-11-30 17:31)
        ✔ 001	ROL @done(23-11-30 17:49)
        ✔ 010	LSR @done(23-11-30 18:12)
        ✔ 011	ROR @done(23-11-30 18:12)
        ✔ 100	STX @done(24-01-08 13:46)
        ✔ 101	LDX @done(24-01-08 14:21)
        ✔ 110	DEC @done(24-01-08 15:59)
        ✔ 111	INC @done(24-01-08 16:01)

    GROUP THREE:
        ✔ 001	BIT @done(24-01-09 16:16)
        ✔ 010	JMP @done(24-01-09 16:16)
        ✔ 011	JMP (abs) @done(24-01-09 16:16)
        ✔ 100	STY @done(24-01-10 14:10)
        ✔ 101	LDY @done(24-01-10 14:10)
        ✔ 110	CPY @done(24-01-10 15:26)
        ✔ 111	CPX @done(24-01-10 15:26)

    CONDITIONALS:
        ✔ 10   BPL @done(24-01-12 16:49)
        ✔ 30   BMI @done(24-01-12 16:49)
        ✔ 50   BVC @done(24-01-12 16:49)
        ✔ 70   BVS @done(24-01-12 16:49)
        ✔ 90   BCC @done(24-01-12 16:49)
        ✔ B0   BCS @done(24-01-12 16:49)
        ✔ D0   BNE @done(24-01-12 16:49)
        ✔ F0   BEQ @done(24-01-12 16:49)

    INTERRUPT/SUBROUTINE:
        ✔ 00   BRK @done(24-01-19 13:16)
        ✔ 20   JSR abs @done(24-01-19 13:16)
        ✔ 40   RTI @done(24-01-19 13:16)
        ✔ 60   RTS @done(24-01-19 13:16)

    SINGLE-BYTE:
        ✔ 08  PHP @done(24-01-19 13:16)
        ✔ 28  PLP @done(24-01-19 13:16)
        ✔ 48  PHA @done(24-01-19 13:16)
        ✔ 68  PLA @done(24-01-19 13:16)
        ✔ 88  DEY @done(24-01-19 13:16)
        ✔ A8  TAY @done(24-01-19 13:16)
        ✔ C8  INY @done(24-01-19 13:16)
        ✔ E8  INX @done(24-01-19 13:16)

        ✔ 18  CLC @done(24-01-19 13:16)
        ✔ 38  SEC @done(24-01-19 13:16)
        ✔ 58  CLI @done(24-01-19 13:16)
        ✔ 78  SEI @done(24-01-19 13:16)
        ✔ 98  TYA @done(24-01-19 13:16)
        ✔ B8  CLV @done(24-01-19 13:16)
        ✔ D8  CLD @done(24-01-19 13:16)
        ✔ F8  SED @done(24-01-19 13:16)

        ✔ 8A  TXA @done(24-01-19 13:16)
        ✔ 9A  TXS @done(24-01-19 13:16)
        ✔ AA  TAX @done(24-01-19 13:16)
        ✔ BA  TSX @done(24-01-19 13:16)
        ✔ CA  DEX @done(24-01-19 13:16)
        ✔ EA  NOP @done(24-01-19 13:16)