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115 lines
4.0 KiB
Plaintext
115 lines
4.0 KiB
Plaintext
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BUGS:
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✔ Branch instructions seem to jump to the wrong place @done(24-01-22 19:08)
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- looks like the offset should be able to be a negative value but it's not
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General:
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✔ Add unit tests for each instruction and address mode @done(23-11-07 19:57)
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☐ Fully implement clock cycle tracking
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☐ Add a disassembler for debugging
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☐ Debug data lookup for instructions
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Test Machine:
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✔ Refactor the OutputConsole and InputConsole into a single Console struct @done(24-07-03 18:39)
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✔ Implement basic input @done(24-07-03 18:39)
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✔ Hello world program @done(24-01-19 17:09)
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✔ Load and run a given program binary @done(24-01-22 17:08)
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CPU:
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Signals:
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✔ Clock @done(23-11-07 20:45)
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✔ Reset @done(23-11-07 20:46)
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✔ irq function @done(24-01-19 13:17)
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✔ nmi function @done(24-01-19 13:17)
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Addressing modes:
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✔ IMP - Implied @done(23-11-07 14:01)
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✔ IMM - Immediate @done(23-11-06 19:01)
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✔ ZP0 - Zero Page @done(23-11-07 14:40)
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✔ ZPX - Zero Page, X @done(23-11-07 14:40)
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✔ ZPY - Zero Page, Y @done(23-11-07 14:40)
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✔ REL - Relative @done(24-01-19 13:17)
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✔ Code @done(23-11-07 20:44)
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✔ Test @done(24-01-19 13:17)
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✔ ABS - Absolute @done(23-11-07 20:25)
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✔ ABX - Absolute, X @done(23-11-07 20:25)
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✔ ABY - Absolute, Y @done(23-11-07 20:25)
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✔ IND - Indirect @done(24-01-10 15:26)
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✔ IZX - Indirect, X @done(24-01-10 15:26)
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✔ IZY - Indirect, Y @done(24-01-10 15:26)
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Instructions:
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GROUP ONE:
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✔ 000 ORA @done(23-11-06 18:55)
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✔ 001 AND @done(23-11-07 13:43)
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✔ 010 EOR @done(23-11-07 13:43)
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✔ 011 ADC @done(23-11-06 19:59)
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✔ 100 STA @done(23-11-07 15:04)
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✔ 101 LDA @done(23-11-06 18:55)
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✔ 110 CMP @done(23-11-09 13:24)
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✔ 111 SBC @done(23-11-09 13:24)
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GROUP TWO:
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✔ 000 ASL @done(23-11-30 17:31)
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✔ 001 ROL @done(23-11-30 17:49)
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✔ 010 LSR @done(23-11-30 18:12)
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✔ 011 ROR @done(23-11-30 18:12)
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✔ 100 STX @done(24-01-08 13:46)
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✔ 101 LDX @done(24-01-08 14:21)
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✔ 110 DEC @done(24-01-08 15:59)
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✔ 111 INC @done(24-01-08 16:01)
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GROUP THREE:
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✔ 001 BIT @done(24-01-09 16:16)
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✔ 010 JMP @done(24-01-09 16:16)
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✔ 011 JMP (abs) @done(24-01-09 16:16)
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✔ 100 STY @done(24-01-10 14:10)
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✔ 101 LDY @done(24-01-10 14:10)
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✔ 110 CPY @done(24-01-10 15:26)
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✔ 111 CPX @done(24-01-10 15:26)
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CONDITIONALS:
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✔ 10 BPL @done(24-01-12 16:49)
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✔ 30 BMI @done(24-01-12 16:49)
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✔ 50 BVC @done(24-01-12 16:49)
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✔ 70 BVS @done(24-01-12 16:49)
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✔ 90 BCC @done(24-01-12 16:49)
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✔ B0 BCS @done(24-01-12 16:49)
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✔ D0 BNE @done(24-01-12 16:49)
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✔ F0 BEQ @done(24-01-12 16:49)
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INTERRUPT/SUBROUTINE:
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✔ 00 BRK @done(24-01-19 13:16)
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✔ 20 JSR abs @done(24-01-19 13:16)
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✔ 40 RTI @done(24-01-19 13:16)
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✔ 60 RTS @done(24-01-19 13:16)
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SINGLE-BYTE:
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✔ 08 PHP @done(24-01-19 13:16)
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✔ 28 PLP @done(24-01-19 13:16)
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✔ 48 PHA @done(24-01-19 13:16)
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✔ 68 PLA @done(24-01-19 13:16)
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✔ 88 DEY @done(24-01-19 13:16)
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✔ A8 TAY @done(24-01-19 13:16)
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✔ C8 INY @done(24-01-19 13:16)
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✔ E8 INX @done(24-01-19 13:16)
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✔ 18 CLC @done(24-01-19 13:16)
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✔ 38 SEC @done(24-01-19 13:16)
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✔ 58 CLI @done(24-01-19 13:16)
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✔ 78 SEI @done(24-01-19 13:16)
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✔ 98 TYA @done(24-01-19 13:16)
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✔ B8 CLV @done(24-01-19 13:16)
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✔ D8 CLD @done(24-01-19 13:16)
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✔ F8 SED @done(24-01-19 13:16)
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✔ 8A TXA @done(24-01-19 13:16)
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✔ 9A TXS @done(24-01-19 13:16)
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✔ AA TAX @done(24-01-19 13:16)
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✔ BA TSX @done(24-01-19 13:16)
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✔ CA DEX @done(24-01-19 13:16)
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✔ EA NOP @done(24-01-19 13:16)
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