General: ✔ Add unit tests for each instruction and address mode @done(23-11-07 19:57) ☐ Fully implement clock cycle tracking ☐ Add a disassembler for debugging ☐ Debug data lookup for instructions CPU: Signals: ✔ Clock @done(23-11-07 20:45) ✔ Reset @done(23-11-07 20:46) ☐ irq function ☐ nmi function Addressing modes: ✔ IMP - Implied @done(23-11-07 14:01) ✔ IMM - Immediate @done(23-11-06 19:01) ✔ ZP0 - Zero Page @done(23-11-07 14:40) ✔ ZPX - Zero Page, X @done(23-11-07 14:40) ✔ ZPY - Zero Page, Y @done(23-11-07 14:40) ☐ REL - Relative ✔ Code @done(23-11-07 20:44) ☐ Test ✔ ABS - Absolute @done(23-11-07 20:25) ✔ ABX - Absolute, X @done(23-11-07 20:25) ✔ ABY - Absolute, Y @done(23-11-07 20:25) ☐ IND - Indirect ☐ IZX - Indirect, X ☐ IZY - Indirect, Y Instructions: GROUP ONE: ✔ 000 ORA @done(23-11-06 18:55) ✔ 001 AND @done(23-11-07 13:43) ✔ 010 EOR @done(23-11-07 13:43) ✔ 011 ADC @done(23-11-06 19:59) ✔ 100 STA @done(23-11-07 15:04) ✔ 101 LDA @done(23-11-06 18:55) ✔ 110 CMP @done(23-11-09 13:24) ✔ 111 SBC @done(23-11-09 13:24) GROUP TWO: ✔ 000 ASL @done(23-11-30 17:31) ✔ 001 ROL @done(23-11-30 17:49) ✔ 010 LSR @done(23-11-30 18:12) ✔ 011 ROR @done(23-11-30 18:12) ☐ 100 STX ☐ 101 LDX ☐ 110 DEC ☐ 111 INC GROUP THREE: ☐ 001 BIT ☐ 010 JMP ☐ 011 JMP (abs) ☐ 100 STY ☐ 101 LDY ☐ 110 CPY ☐ 111 CPX CONDITIONALS: ☐ 10 BPL ☐ 30 BMI ☐ 50 BVC ☐ 70 BVS ☐ 90 BCC ☐ B0 BCS ☐ D0 BNE ☐ F0 BEQ INTERRUPT/SUBROUTINE: ☐ 00 BRK ☐ 20 JSR abs ☐ 40 RTI ☐ 60 RTS SINGLE-BYTE: ☐ 08 PHP ☐ 28 PLP ☐ 48 PHA ☐ 68 PLA ☐ 88 DEY ☐ A8 TAY ☐ C8 INY ☐ E8 INX ☐ 18 CLC ☐ 38 SEC ☐ 58 CLI ☐ 78 SEI ☐ 98 TYA ☐ B8 CLV ☐ D8 CLD ☐ F8 SED ☐ 8A TXA ☐ 9A TXS ☐ AA TAX ☐ BA TSX ☐ CA DEX ☐ EA NOP